And Imec will examine the consequences for a design philosophy for 3D chips called system technology cooptimization (STCO).
It looks like Intel will be talking about backside power’s consequences for 3D devices. This scheme, called backside power delivery, has all sorts of consequences that chip companies are working out. Beginning as soon as late 2024, chipmakers will start building power-delivery interconnects beneath the silicon, leaving data interconnects above. One is a change to the placement of a subset of chip interconnects. Generally, manufacturers are striving to increase the density of the vertical connections between chips.
Increasing the number of transistors you can squeeze into a given area by stacking up chips (called chiplets in this case) is both the present and future of silicon.
